David Paz

.MIT Department: Electrical Engineering and Computer Science

Undergraduate Institution: University of California, San Diego

Faculty Mentor: Arvind Arvind

Research Supervisor: Andy Wright

Website: LinkedIn


I am junior in Computer Engineering at the University of California, San Diego. Some of my current research involves high performance computing (HPC) containerization at the San Diego Supercomputer Center, and sensor design for a program called i-Trek. I plan to pursue a PhD in Computer Science and emphasize my research on Intelligent Systems. When I am not at school or at work, I spend my free time with my family, and maintaining my car. I also enjoy taking panoramic pictures with my camera and practicing Muay Thai and Tae Kwon Do.

2017 Poster Presentation

2017 Research Abstract

Optimizing Two-Dimensional Convolution Accelerators for Area, Energy, and Flexibility

David Paz, Department of Electrical and Computer Engineering, University of California, San Diego, San Diego, CA

Andy Wright, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA

Advisor – Prof. Arvind, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Cambridge, MA

Two-dimensional convolution calculations have direct applications in image processing, filtering and pattern detection. Highly optimized hardware accelerators are capable of increasing performance on very specific computational tasks by large factors over sequential software applications. These accelerators are often optimized for instructions per clock cycle. However, one important aspect of hardware accelerator design that is often overlooked relates to application flexibility. For instance, Convolution Neural Network (CNN) accelerators are designed with a predefined number of accelerator cores and application specific tasks that may not be modified dynamically and can be expensive.

This study aims to develop energy efficient and flexible two-dimensional convolutional accelerators ideal for IoT and smaller devices to provide significant performance gains over sequential computations and flexibility over application-specific accelerators such as CNN accelerators. Bluespec System Verilog (BSV) has been used to develop the accelerator by implementing pipelined 3D Tree structures. These structures have been fully incorporated into a three-stage pipelined RISC-V processor, and they are capable of interacting directly with memory and exploit temporal locality to maximize performance with minimal energy and area cost, while providing users with fine-grain control of their kernel and matrices.