Abraham Gonzalez

MIT Department: Electrical Engineering and Computer Science

Undergraduate Institution: University of Texas, Austin

Faculty Mentor: Duane Boning

Research Supervisor: Chris Lang

Website: LinkedIn


I was born and raised in El Paso, Texas. I am currently a 4th year student at the University of Texas at Austin majoring in Electrical and Computer Engineering. My research interests include improving efficiency and speed in microprocessors. My goal is to be a part of the next wave of computer innovation while making computers more widely available to all. I plan to attend graduate school to pursue a Ph.D. in Computer Engineering. My current hobbies are attending concerts, discovering new music, and playing board games.

2017 Poster Presentation

2017 Research Abstract

A Machine Learning Approach to Modeling Copper Electroplating Process Variations in Integrated Circuit Redistribution Layers

Abraham Gonzalez, Department of Electrical and Computer Engineering, University of Texas at Austin.

Chris Lang, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology

Duane Boning, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology

Current semiconductor manufacturing research is often focused on improving integrated circuit (IC) technologies to reduce fabrication costs and increase IC yield. One component of interest is the redistribution layer (RDL), a wafer-level packaging layer that allows multiple different IC chips or die to be integrated into a single package. Typically, the copper interconnects within the RDL are fabricated with an electrochemical plating (ECP) process that is prone to pattern dependent variations in height. These non-uniformities in the copper must be planarized using an expensive chemical mechanical polishing process (CMP) in order to prevent subsequent lithography issues. Predicting these variations may enable circuit layout modification to reduce post-ECP variations such that the CMP step can be avoided.

Previous work used highly structured statistical and physically-motivated models to estimate these copper heights. In order to explore other models and their accuracies, in this work we consider using and optimizing generic neural networks to accurately predict the height of the plated copper as a function of the interconnect layout without needing large amounts of training data or long runtimes. This is done by optimizing the depth, width, and type of layers to improve the prediction, and by us giving differing input layouts while minimizing the time needed to train the model. Implications of this research include understanding the tradeoffs in machine learning, statistical and physically-based models with respect to accuracy, data needs, and model development effort for applications in semiconductor manufacturing, as well as contributing a novel neural network-based model for the prediction of variation and reduction of cost in the fabrication of IC RDL layers.